The latency (time spent waiting) for memory access, both to write to memory and to read from memory, is often a problem for software programs. In current computers, processor cycles are much shorter than the time for memory access. Further, the problem is becoming more severe. Processor speed is increasing exponentially, and memory access is increasing only gradually.
One partial remedy to the problem of memory access latency is a hierarchy of memories. The main memory has a large capacity and is slowest. On top of this are several layers of successively smaller, faster memories, or caches.
The current use of caches presents problems. A read from a cache may fail when the cache does not contain the desired data. The data must then be accessed from the slow main memory. An attempt to write data exclusively to a cache may not be permitted. Data from the processor can be written to the cache and then pushed to main memory. Thus, there is the latency of writing to the slower main memory. Further, there can be a latency in accessing the data. The data written to a cache may be replaced by other data before the replaced data is accessed. When this occurs, the replaced data is written to main memory. To then utilize this data, the data must be accessed from main memory.
Therefore, there is a need for a method for a processor to write data to a cache or other fast memory without also writing it to main memory. Further, the method must guarantee that the data remains in the cache or other fast memory until it has been used.